The conventional video display control circuit comprises a central processor unit (CPU) for controlling operation of the circuit, a character read only memory (C-ROM) for storing data of characters to be displayed, a display control signal generating circuit for generating a display control signal in accordance with data of characters supplied from the C-ROM, a C-ROM pointer for designating an address of the C-ROM where a character to be displayed is stored, a video random access memory (V-RAM) for storing addresses of the C-ROM by which the C-ROM pointer designates an address of the C-ROM, and a V-RAM pointer for designating an address of the V-RAM where an address data to be supplied to the C-ROM pointer is stored.
In operation, the V-RAM pointer designates an address of the V-RAM which is determined by a scanning position of the screen, so that a starting address of a character to be displayed is read from the V-RAM to be supplied to the C-ROM pointer. Then, the character data are read from the C-ROM which is accessed by the C-ROM pointer providing the starting address and increased addresses, and are supplied to the display control signal generating circuit, so that the character is displayed on the screen of the television set.
In this video display control by use of the CPU, data are re-written into the V-RAM during horizontal and/or vertical blanking retrace intervals to suppress the collision between the read-out of the V-RAM data and the re-writing of data into the after the finish of each scanning line display and/or each frame display.
According to the conventional video display control circuit, however, there is a disadvantage in that flickering or momentary black-out of the display may occur, because the re-writing operation does not finish during the vertical blanking retrace interval when a great amount of V-RAM data are re-written under the situation where operation other than the V-RAM data re-written is carried out during the limited interval. In order to overcome this disadvantage, another conventional video display control circuit has two V-RAMs which are used alternately for reading and writing, such that data are written one of tile V-RAMs while data are written into the other V-RAM. However, such a hardware structure has a disadvantage in cost.